用verilog实现三八译码器代码：
module decoder(data_out,en,data_in);
input [2:0] data_in;
input en;
output reg [7:0] data_out;
always @(en or data_in)
begin
if(en==1)
case(data_in)
3'b000:data_out=8'b0000_0001;
3'b001:data_out=8'b0000_0010;
3'b010:data_out=8'b0000_0100;
3'b011:data_out=8'b0000_1000;
3'b100:data_out=8'b0001_0000;
3'b101:data_out=8'b0010_0000;
3'b110:data_out=8'b0100_0000;
3'b111:data_out=8'b1000_0000;
endcase
else
data_out=8'b0000_0000;
end
endmodule
三八译码器测试文件代码：
`timescale 1ns/1ps
module decoder_test();
reg [2:0] data_in;
reg en;
wire [7:0] data_out;
decoder i1(.data_in(data_in),
.data_out(data_out),
.en(en)
);
initial
#100 $stop;
initial
#10 data_in=0;
initial
#10 en=0;
initial
#15 en=1;
always
#10 data_in=data_in+1;
endmodule
利用三八译码器转四-十六译码器：
module decoder4_16(data_out1,data_out2,data_in1,data_in2);
input [2:0] data_in1;
input data_in2;
output [7:0] data_out1,data_out2;
wire [7:0] data_out1,data_out2;
assign data_in3=~data_in2;
decoder l(data_out1,data_in2,data_in1);
decoder h(data_out2,data_in3,data_in1);
endmodule
四-十六译码器测试代码（采用调用子模块的方法）：
`timescale 1ns/1ps
module decoder4_16_test();
reg [2:0] data_in1;
reg data_in2;
wire [7:0] data_out1,data_out2;
decoder4_16 i1(
data_out1,
data_out2,
data_in1,
data_in2
);
initial
begin
data_in1=3'b000;
data_in2=1'b0;
end
always #80 data_in2=~data_in2;
always
#10 data_in1=data_in1+1;
endmodule
运行结果：
熊哥的方法：
module decoder(data_in, data_out1,data_out2);
input [3:0] data_in;
reg [2:0] data_in1;
output reg [7:0] data_out1;
output reg [7:0] data_out2;
always @*
begin
data_in1=data_in[2:0];
if(data_in[3]==0)
begin
data_out2=8'b0000_0000;
case(data_in1)
3'b000:data_out1=8'b0000_0001;
3'b001:data_out1=8'b0000_0010;
3'b010:data_out1=8'b0000_0100;
3'b011:data_out1=8'b0000_1000;
3'b100:data_out1=8'b0001_0000;
3'b101:data_out1=8'b0010_0000;
3'b110:data_out1=8'b0100_0000;
3'b111:data_out1=8'b1000_0000;
endcase
end
else
begin
data_out1=8'b0000_0000;
case(data_in1)
3'b000:data_out2=8'b0000_0001;
3'b001:data_out2=8'b0000_0010;
3'b010:data_out2=8'b0000_0100;
3'b011:data_out2=8'b0000_1000;
3'b100:data_out2=8'b0001_0000;
3'b101:data_out2=8'b0010_0000;
3'b110:data_out2=8'b0100_0000;
3'b111:data_out2=8'b1000_0000;
endcase
end
end
endmodule
测试代码：
`timescale 1ns/1ps
module decoder_test();
reg [3:0] data_in;
wire [7:0] data_out1;
wire [7:0] data_out2;
decoder i1(.data_in(data_in),
.data_out1(data_out1),
.data_out2(data_out2)
);
initial
#180 $stop;
initial
#10 data_in=0;
always
#10 data_in=data_in+1;
endmodule
运行结果：